GIMPS (Prime95) benchmarks

Benchmarks » AMD » EPYC » EPYC 7251

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AMD – EPYC

EPYC 7251

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	Performance
Cores	8
Threads	16
Clock (min)	2100
Clock (max)	2900
Cache (L1)	96 kB (x8)
Cache (L2)	512 kB (x8)
Cache (L3)	32.00 MB total

Performance

Cores

Threads

Clock (min)

2100

Clock (max)

2900

Cache (L1)

96 kB (x8)

Cache (L2)

512 kB (x8)

Cache (L3)

32.00 MB total

Code Name	Naples
Process	14 nm
TDP	120 W
Socket	Socket TR4
Release Date	2017-Jun-29

Code Name

Naples

Process

14 nm

TDP

120 W

Socket

Socket TR4

Release Date

2017-Jun-29

Link: CPW	CPU World
Link: TPU	TechPowerUp

Link: CPW

CPU World

Link: TPU

TechPowerUp

Throughput

2048K	2560K	3072K	3584K	4096K	5120K	6144K	7168K	8192K
722.246	536.329	442.661	319.250	296.022	249.068	201.342	178.482	152.659

2048K

2560K

3072K

3584K

4096K

5120K

6144K

7168K

8192K

722.246

536.329

442.661

319.250

296.022

249.068

201.342

178.482

152.659

0M	<	10¹⁰	All tracked exponents
0M	<	2³²	GPU TF range
0M	<	1000M	PrimeNet range
0M	<	193M	low-PrimeNet, low-res
0M	<	385M	low-PrimeNet, high-res
50M	<	146M	PrimeNet wavefront

processor
codename
cores
cores_efficient
cores_efficient_lp
threads
threads_efficient
threads_efficient_lp
clock_min
clock_min_efficient
clock_min_efficient_lp
clock_max
clock_max_efficient
clock_max_efficient_lp
socket
process
cache_l0
cache_l1
cache_l1_efficient
cache_l1_efficient_lp
cache_l2
cache_l2_efficient
cache_l2_efficient_lp
cache_l3
cache_l3_efficient
cache_l3_efficient_lp
cache_l4
tdp
gpu_model
gpu_clock
release_price
release_date
release_date_precision
cpuid
sspec
part_numbers
intel_mm
url_techpowerup
url_cpuworld
url_x86guide
url_manufacturer